Performance Analysis of Error Detection and Correction Techniques for Communication Modules

Abstract

The error detection and error correction techniques play a major role in the digital data transformation over reliable communications. They are suitable techinques to implement them in deferrent signal conditions in the digital communication. In this work, the various error detection and error correction methods were analyzed based on power and area. The design was simulated and synthesized using synopsys verilog compiler simulator (VCS) and cadence register transfer language (RTL) compiler and cadence encounter too which were used for application specific integrated circuit (ASIC) implementation.